Memory devices are ubiquitous in a wide variety of modern electronic devices such as cellular phones, personal computers, laptops, personal digital assistants, camcorders, voice recorders, media players, and portable storage devices. Non-volatile memory devices (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and Flash memory) do not require power to retain information, and have become a useful and popular mechanism for storing, transporting, sharing, and maintaining data. Flash memory has become a popular device for consumer electronics, due in part, because it combines the benefits of EPROM (high density and low cost) with the benefits of EEPROM (electrical erasability).
Multiple storage flash memory cells, also known as multi-bit, multi-cell, and/or multi-level memory cells, have been developed to meet the demand for higher density storage devices. Multiple storage flash memory technology enables a single flash memory transistor to store more than one bit, and thus more than two logic states, in the transistor. For example, a 2-bit flash memory transistor can store four logic states (e.g., 00, 01, 11, 10), each state represented by a quantized voltage or current level. Logic states can be stored (i.e., erased or programmed) into a multiple storage flash memory transistor by controlling a level of electrical charge applied to or removed from one or more floating gates of the transistor.
One concern with conventional multiple storage flash memory technology is that programming or erasing a characteristic (e.g., logic state) of one bit of a memory cell can indeterministically disturb characteristics of other bits of the memory cell, reducing memory cell program/erase accuracy. Another concern with conventional multiple storage flash memory technology is that this reduced memory cell program/erase accuracy reduces control over the distribution of stored memory cell characteristics. For example, logic states are determined, or sensed, as a function of distributions of stored logic states; therefore, memory read errors can result when distributions of stored logic states associated with different bits of one or more memory cells overlap.
It is therefore desirable to have systems and methods that increase device reliability by improving the accuracy of storing characteristics in multiple storage flash memory cells. Further, it is desirable to reduce multiple storage flash memory cell read errors by more effectively controlling distributions of stored memory cell characteristics.